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Title:
APPLICATION LIQUID FOR FORMATION OF INTERLAYER PACKED BED LAYER OF THREE-DIMENSIONAL INTEGRATED CIRCUIT AND THREE-DIMENSIONAL INTEGRATED CIRCUIT MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2013145841
Kind Code:
A
Abstract:

To provide an application liquid for formation of an interlayer packed bed of a three-dimensional integrated circuit, which can form, at a time of a B-stage heat treatment, a homogenous B-stage film from a coated film formed on a semiconductor substrate by evaporating and removing an organic solvent at a moderate evaporation rate by application; and which can form a favorable interlayer packed bed layer by heat hardening the B-stage film.

An application liquid for formation of an interlayer packed bed layer of a three-dimensional integrated circuit, includes: a thermosetting resin (A) which has a heat transfer coefficient of 0.2 W/mK and over, melt viscosity at 50°C of 500 Pa s and over, and melt viscosity at 120°C of 100 Pa s and under; an inorganic filler (B) which has a heat transfer coefficient of 2 W/mK and over, an average grain size of not less than 0.1 μm and not more than 5 μm, and a maximum grain size of 10 μm and under; a surface-active agent (D); and an organic solvent (E) which has a boiling point of 120°C and over.


Inventors:
KAWASE YASUHIRO
IKEMOTO SHIN
Application Number:
JP2012006292A
Publication Date:
July 25, 2013
Filing Date:
January 16, 2012
Export Citation:
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Assignee:
MITSUBISHI CHEM CORP
International Classes:
H01L21/60; C08K3/00; C08K5/09; C08K5/29; C08K5/3445; C08L101/12; C09D7/12; C09D201/00; H01L21/52; H01L25/065; H01L25/07; H01L25/18
Attorney, Agent or Firm:
Tsuyoshi Shigeno