To facilitate verification, improve accuracy and improve efficiency in verification of an arbitration circuit (arbiter).

A plurality of virtual master models are provided connected to the verification target arbitration circuit. The virtual master models have functions of starting at optional timing, changing density of a request signal output to the arbitration circuit, needing no input data, stopping temporarily, operating at harsher conditions than an actual master circuit, activating at random timing, issue a request signal at random timing or the like.