Title:
ＮＡＮＤメモリプログラミングのためのアーキテクチャおよび方法
Document Type and Number:
Japanese Patent JP7451773
Kind Code:
B2
Abstract:
In a method of programming a memory device, inhibit information is stored to first latch structures and second latch structures. A first state programming voltage is applied to data lines of memory cells of the memory device to program the memory cells to the first state. A first state verification voltage is applied to the data lines of the memory cells to perform a first state verification operation on the memory cells. The first state verification operation verifies first state threshold voltages of the memory cells based on a first target value and also generates failure pattern data of the first state verification operation. The failure pattern data is then stored to the second latch structures. Further, a first level adjusted verification voltage is applied to the data lines of a portion of the memory cells that fails the first level verification operation to perform a first level adjusted verification operation.
Inventors:
Wei Jun Wang
Application Number:
JP2022578921A
Publication Date:
March 18, 2024
Filing Date:
September 24, 2020
Export Citation:
Assignee:
Yangtze Memory Technologies Co.,Ltd.
International Classes:
G11C11/56; G11C16/04; G11C16/10; G11C16/24; G11C16/34
Domestic Patent References:
| JP2008535138A | ||||
| JP2018530096A | ||||
| JP2003196988A |
Foreign References:
| US20140119126 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Shinya Mihiro
Tatsuhiko Abe
Shinya Mihiro
Tatsuhiko Abe