PURPOSE: To reduce the amount of hardwares to be added and to efficiently perform arithmetic operations at the time of performing division by using a DSP.
CONSTITUTION: This unit is provided with the arithmetic and logic circuit 4 of (n) bits capable of controlling whether to perform addition or subtraction by signals indicating the positive/negative of an arithmetic result performed one before, the register 2 of (n) bits for tentatively storing the output data at the arithmetic and logic circuit 4, the register 1 of (n) bits for outputting a divisor to the arithmetic and logic circuit 4, (n) stages of shift register 5 for successively storing the signals indicating the positive/negative of the arithmetic result of the arithmetic and logic circuit 4 and a shifter 3 for shifting the data of the register 2 to left for one bit, inserting the data of the most significant bit of the shift register 5 to a least significant bit and performing output to the arithmetic and logic circuit 4. The shitter conventionally provided with the bit length of 2n is replaced with the shifter 3 provided with an (n) bit length and the shift register 5 provided with the bit length of (n).
ISHIKAWA TOSHIHIRO
FUJIMOTO YUKIHIRO
MINAMIDA TOMOAKI
