PURPOSE: To begin a read at the starting address of an indirect branch instruction even if the number of address bit of firmware exceeds that of arithmetic bits of a bit-slicing logical operating circuit (ALU), by processing a fetch cycle and an execution cycle simultaneously.

CONSTITUTION: For example, an instruction N holds the starting address of an indirect branch destination. As a clock C rises, the output of an instruction N-1 in a control memory 3 is held in a latch 4 and at the same time, the address of the instruction N appears in a program counter 2. High-order eight-bit outputs A and B in the latch 4 are analyzed by a decoder 5 to generate a drive signal for a driver 6. An output C obtained by the control memory 3 is inputted to an ALU1 via the driver 6 and at the same time, the instruction N is latched by the latch 4. The high- order eight-bit A and B of the instruction N are analyzed by the decoder 5. The low-order eight-bit outputs D and E and inputted to the ALU1 via a driver 7. Consequently, the starting address of the indirect branch destination is read in the ALU1 to execute the indirect branch instruction.