演算装置、積和演算装置、積和演算回路、及び積和演算システム

Japanese Patent JP7420072

B2

An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Electrical signals are input to the plurality of input lines. The multiply-accumulate operation device includes a pair of output lines, a plurality of multiplication units including a weight unit that generates, on the basis of the electrical signals input to the plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on the basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines, an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units, and an output unit that outputs, on the basis of the accumulated charges, a multiply-accumulate signal representing a sum of the multiplication values.

Takashi Morie
Masatoshi Yamaguchi
Right of Tamukai

JP2020531244A

January 23, 2024

July 05, 2019

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Sony Group Corporation

G06G7/16; G06G7/60; G06N3/063

JP2007241475A
JP2007066258A
JP4237364A
JP2133888A

WO2018034163A1

森江隆,腦型アナログ演算と専用集積回路,人工知能,人工知能学会,2018年01月01日,第33巻、第1号,p.39-44、ISSN 2188-2266

Patent Attorney Corporation Minami Aoyama International Patent Office
Junichi Ohmori
Mitsuru Takahashi
Teppei Nakamura
Akira Orii
Masayoshi Sekine
Ayako Kaneko
Shintaro Kanayama
Ayako Chiba
Tomohisa Shiraka

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