PURPOSE: To provide a microprocessor circuit, architecture and method for digital data processing, especially, for digital image/graphics processings.
CONSTITUTION: An arithmetic logic unit(ALU) can be divided into plural blocks 301-304 and the respective blocks form one output of related partial set of inputs. A state detector generates a single bit state signal from the outputs of respective blocks and stores it in a flag register. The new state signal may be overwritten on the preceding state signal, or the stored bit may be rotated and the new state signal can be stored as well. Multiplexers 311-314 between the carry-out of respective basic blocks and the carry-in of adjacent basic blocks multiplex the both or do not multiplex them, while depending on the selected number of blocks. The carry-out from the respective basic blocks, not to be multiplexed with the adjacent basic blocks, is supplied to the flag register. The selected bit of the flag register is expanded by an expansion circuit and formed into 3rd input to the ALU.
NIKORASU INGU SHIMONZU
KAARU EMU GUTSUTAGU
ROBAATO JIEI GOOBU
JIERIMAIAA II GOORUSUTON
KURISUTOFUAA JIEI RIIDO
SHIDONII DABURIYUU POORANDO
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