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Patent Searching and Data


Title:
ARITHMETIC PROCESSOR
Document Type and Number:
Japanese Patent JP2004147103
Kind Code:
A
Abstract:

To suppress the operation speed of an LSI to a low level, and realize miniaturization, light weight and low cost of a mobile terminal.

Adders 120a-1 to 120a-4 obtain channel estimation coefficients updated on the basis of a multiplication result of a multiplier 110a, ground, the count value of a 2-bit counter 130 or a select signal 600. The 2-bit counter 130 generates a 2-bit numeral value with a predetermined number of clocks, outputs each bit to the adders 120a-2, 120a-3 respectively, and also outputs the 2-bit count value to a memory 140. The memory 140 outputs the channel estimation coefficients before updating to the adders 120a-1 to 120a-4 on the basis of the count value of the 2-bit counter 130 and the select signal 600, and also holds channel estimation coefficients updated in a predetermined memory area on the basis of the count value of the 2-bit counter 130.


Inventors:
YAMANAKA RIYUUTAROU
Application Number:
JP2002309976A
Publication Date:
May 20, 2004
Filing Date:
October 24, 2002
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03H21/00; H04B3/10; H04L25/02; H04L25/03; (IPC1-7): H04B3/10
Attorney, Agent or Firm:
Koichi Washida