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Patent Searching and Data


Title:
ARITHMETIC SYSTEM FOR DIGITAL SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JPS6386023
Kind Code:
A
Abstract:

PURPOSE: To decrease the number of processing steps by using a single bit of an idle field of a microcode to add +1 and -1 to the 15th bit of a computing element.

CONSTITUTION: A digital signal processor consists of a program ROM 1, a data ROM 2, a RAM 3, an address counter 4, saving registers 5 and 6 for counter 4, the storing (output) registers 12 and 13 for arithmetic result of a computer element 11. A microcode for this arithmetic includes a field to prescribe the contents of the arithmetic to be processed and a field to prescribed the contents to be used for operations. Then a single bit of an idle field of the microcode is used to control +1 and -1 to be added to the 0-th bit as well as +1 and -1 to be added to the 15th bit respectively.


Inventors:
SUNAGA JUNKO
Application Number:
JP23361886A
Publication Date:
April 16, 1988
Filing Date:
September 30, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F7/00; G06F9/22; G06F17/10; (IPC1-7): G06F7/00; G06F9/22
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)