To provide an arithmetic unit capable of executing highly accurate operation at a high speed even when the number of storage means is small.

When the input data 1 of data DIN0 to DINm-1 are inputted, an input data judging circuit 2 judges the range of bit length of the input data 1 and outputs a selection signal 3. The input data 1 are applied to the address inputs of plural ROMs, i.e., a ROM3 4, a ROM2 5 and a ROM1 6 having addresses to be the range of prescribed bit length capable of obtaining a square root of necessary accuracy. A ROM output selection circuit 7 selects any one of the ROMs 4 to 6 based on the selection signal 3 and outputs a square root value substituted in each of the ROMs 4 to 6 as a square root output f (x) 8. When the input data 1 has bits larger than the address space of respective ROMs 4 to 6 consisting of n bits, the range of the bit length of the input data 1 is divided to respective ROMs 4 to 6. Consequently a square root value can be instantaneously obtained by a table corresponding to the addresses of these ROMs 4 to 6 without reducing accuracy.