To minimize the processing load of each processor (CPU) with increased flexibility of distributed processing, and to attain significant reduction in power consumption by reduction of operation frequency or reduction of power supply voltage.

This asymmetric multiprocessor 100 comprises a hardware resource arbitration part 110 which performs arbitration of a request signal from each CPU core 101a, 101b, the signal requesting use permission of an optional hardware accelerator; a signal processing content selection part 111 which selects a signal processing content of a dynamic configuration type signal processor part 107 slave-connected thereto; a clock skew arbitration part 112 which performs a control for optionally shifting a clock phase relation each between groups; and clock delay generation parts 113a-113g which delay a clock signal based on a clock skew selection enable signal 114.

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