PURPOSE: To use the system for error correction processing after synchronization establishment or abort processing of erroneous cells while attaining low speed operation by the parallel processing as the cell synchronization system by receiving an ATM cell flow, decoding an output of a divider to generate a cell synchronizing pulse for cell synchronization processing thereby eliminating the need for addition of a storage circuit to store cell headers.

CONSTITUTION: An 8-bit ATM cell flow is given to 5-stage D flip-flop circuits 1a-1e and outputted to an adder circuit 5a via a residue arithmetic circuit 3. The adder 5a calculates exclusive OR between the output of the residue arithmetic circuit 3 and the received cell and the result of arithmetic operation is given to the D flip-flop circuit 1f via an adder 5b. An output of the D flip-flop circuit 1f is given to a parallel processing CRC arithmetic circuit 7 and a decoder 9. An output of the CRC arithmetic circuit 7 is given to the adder 5b and a cell synchronizing pulse is outputted from the decoder 9.