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Title:
ATM-LAN FRAME PROCESSING CIRCUIT
Document Type and Number:
Japanese Patent JP2000115175
Kind Code:
A
Abstract:

To improve test pattern efficiency by extracting an ATM cell data string from frame data for testing for which the data length of an area for storing ATM cell data is reduced and testing the same overhead communication function as a real mode.

At the time of a test mode, the data length of an SPE area for storing the ATM cell data is reduced to 51 bytes × 9 rows to 261 bytes ×9 rows in a normal transmission frame. An overhead area is kept as 9 bytes ×9 rows as it is. A frame header position detection circuit 1 detects the position of a frame header and outputs overhead timing signals based on overhead data. In this case, while it is 2430 clock cycles in the real mode, it becomes 540 clock cycles in the test mode. An SPE area data extraction circuit 3 detects the leading byte position of the SPE area based on the overhead timing signals and extracts SPE area data.


Inventors:
YOSHITSU TAKUYA
Application Number:
JP27785698A
Publication Date:
April 21, 2000
Filing Date:
September 30, 1998
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
H04J3/00; H04L12/26; H04L12/28; H04Q3/00; (IPC1-7): H04L12/28; H04J3/00; H04Q3/00
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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