To improve the reliability of circuit operation by automatically adjusting the output timing of a timing adjusted signal and improve the operation speed by effectively making use of an increase in the margin of operation timing.

A timing setting circuit 12 generates a plurality of timing adjusted signals which are in different output timing. A signal delay judging circuit 18 monitors the degree of delay of the timing adjusted signals which are actually outputted and judges the degree after the delay. A data selector 14 selects one of the timing adjusted signals of the timing setting circuit 12 according to the judgement result. A signal output circuit 16 is an output buffer, etc. The output timing of the signals can automatically be adjusted.