To control the timing of a semiconductor integrated circuit by varying the power source potential of cells.

An apparatus is equipped with an initial power source setting means 9 which sets the initial value of the power source potential of the cells, an arranging and wiring means 10 which arranges the cells and performs rough wiring and detailed wiring according to a net list 3 and timing restriction information 4, a timing verifying means 11 which verifies the timing of a specified path according to layout information of a specified state of the arrangement and wiring, and a power source changing means 13 which prescribes change of the power source potential of a cell which has improper timing when the cell is detected. When a cell having improper timing is detected, the arranging and wiring means 10 optimizes a layout according to change of the power source potential of the cells prescribed by the power source change means 13 and the timing verifying means 11 verifies the timing of the specified path according to the optimized layout information.