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Title:
AUTOMATIC EQUALIZER
Document Type and Number:
Japanese Patent JPS5675732
Kind Code:
A
Abstract:

PURPOSE: To reject the interference between codes of an automatic equalizer, by controlling the slope gain with the result of correlation between the output waveform of equalizer and the waveform delaying it and controlling the flat gain with the peak value of the waveform of equalizer output.

CONSTITUTION: Since the gain of a variable gain circuit is (a), the gain of a variable gain circuit 4 is (b) and the frequency characteristics of the differentiating circuit 8 is jf/fo, then the characteristics of the output of an adder 5 is expressed in equation (1), [where; fo is a frequency twice the Nyquist frequency, (f) is frequency, (a) is flat gain of the equalizer, and (b) is the slope gain]. If the gain (b) is excessive, the output of a correlator 8 is small and the gate voltage of FETF2 is lowered, then the resistance between the source and drain is greater and the gain (b) is smaller. Conversely, if the gain (b) is small, similarly the (b) is greater. The gain (b) converges to an optimum value. When the gain (b) further converges to the optimum value, the gain (a) also converges to the optimum value with the control of a peak voltage detection circuit 6 and a controlling circuit 9. Thus, the gains (a) and (b) converge to the optimum value, the interference between codes can be rejected.


Inventors:
YAMAGUCHI MASARU
AKASHI FUMIO
KOYAMA TOORU
Application Number:
JP15267079A
Publication Date:
June 23, 1981
Filing Date:
November 26, 1979
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03H7/01; H03H21/00; H04B3/06; H04L25/03; (IPC1-7): H03H7/01; H03H21/00; H04B3/04



 
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