Title:
AUTOMATIC EQUALIZING CIRCUIT
Document Type and Number:
Japanese Patent JP3060884
Kind Code:
B2
Abstract:
PURPOSE: To provide an automatic equalizing circuit of partial response (PR) 4-detection system with simple configuration.
CONSTITUTION: Comparators C1 and C2 respectively compare an equalizer output yn with reference values v1 and v2 so as to discriminate whether or not the signal yn is '1', '0' or '-1' and comparators C3-C5 respectively discriminate whether the equalizer output yn is larger than reference values v3, v4 and v5. Based on respective outputs a+, a-, e+1, e0, e-1, a data extraction/equalization error detection block 7 detects deviation from an ideal equalized waveform and outputs tap coefficient correct signals CT+1, CT0, CT-1, CN0 and CN-1. The respective analog added values of signals (CT+1, CN+1), (CT0, CN0) and (CT-1, CN-1) are respectively calculated by adder circuits 8+1, 80 and 8-1 and averaged, and based on these respective average values, tap coefficients C+1, C0 and C-1 are respectively adapted through buffers 9+1, 90 and 9-1.
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Inventors:
Ryo Nakano
Application Number:
JP10013695A
Publication Date:
July 10, 2000
Filing Date:
March 31, 1995
Export Citation:
Assignee:
Victor Company of Japan Ltd.
International Classes:
G11B20/10; H03H21/00; H04B3/04; H04L1/00; H04L25/03; H04L25/497; (IPC1-7): H04L25/03; H04B3/04; H04L25/497
Domestic Patent References:
| JP6125245A | ||||
| JP644508A | ||||
| JP63224407A | ||||
| JP6116630A |
Attorney, Agent or Firm:
Nihei Masataka