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Patent Searching and Data


Title:
AUTOMATIC LAYOUT METHOD FOR LOGICAL CELL BLOCK
Document Type and Number:
Japanese Patent JP2000276518
Kind Code:
A
Abstract:

To shorten the processing time needed for laying out logical cell blocks by preparing a layout rule to lay out these cell blocks from the outside to the inside of a decided layout area along the outer circumference of the layout area and in the order of larger sizes of cell blocks before an automatic layout operation.

The layout rule is set to lay out the logical cell blocks from the outside to the inside of a decided layout area along the outer circumference of the layout area and in the order of larger sizes of the cell blocks before an automatic layout operation. In this method, the sizes of logical cell blocks to be laid out are retrieved in step S1-a in the prescribed layout area and before an automatic layout operation and then a layout sequence is decided in the order of larger sizes of cell blocks in step S1-b. In steps S1-c and S1-d, a layout rule is set to decide the layout positions of those cell blocks according to the layout sequence decided in the step S1-b. Then the automatic layout is carried out in step S1-e and this step S1-e is repeated in step S1-f until all logical cell blocks are laid out according to the layout rule.


Inventors:
WADATSU YURIKO
Application Number:
JP8538199A
Publication Date:
October 06, 2000
Filing Date:
March 29, 1999
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G06F17/50; H01L21/82; (IPC1-7): G06F17/50; H01L21/82
Attorney, Agent or Firm:
Shigeru Noda