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Patent Searching and Data


Title:
AVERAGE LEVEL REMOVING SYSTEM
Document Type and Number:
Japanese Patent JPS5748663
Kind Code:
A
Abstract:

PURPOSE: To eliminate the need for a costly high speed A/D converter of multibits and lower the cost of production by obtaining the digital value used for calculation of average values by low speed A/D conversion.

CONSTITUTION: The output of a low speed A/D converter 61 inputted with an analog signal (a) is inputted to an average level operating circuit 52 consisting of plural registers and adders, and a digital average signal (b') is latched by latch circuits 63, 64. The digital average signal (f') thereof is again converted to an analog signal (f) by a low speed D/A converter 65, and the difference between the analog signal (f) and the analog signal (a) is amplified by a differential amplifier 66. This signal (g) is converted by a high speed A/D converter 67, by which a digital signal (g') for flaw detection is obtained. Thereby, inexpensive circuits are used and the production cost for the device is lowered.


Inventors:
KITAMURA SHINICHI
Application Number:
JP12398680A
Publication Date:
March 20, 1982
Filing Date:
September 09, 1980
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G01R19/12; G01N21/89; G01N21/892; G01S3/78; G01S3/781; G06J1/00; H04N5/14; (IPC1-7): G01N21/88; G01R19/12; G01S3/78; H04N5/14