Title:
BASE DIE TESTER
Document Type and Number:
Japanese Patent JP3240395
Kind Code:
B2
Abstract:
PURPOSE: To enhance the reliability of individual IC function in a circuit assembly and the quality of a device by soldering a large number of microbumps to metal pads on an interconnection structure, while arranging at the pattern position corresponding to the pattern of the contact pads of a bare die to be tested.
CONSTITUTION: A multipalyer interconnection structure (substrate) 10, comprising a ground plane 13, a power plane 14 and two signal layers 15, is formed on a silicon substrate 16 by thin-film technology. Micro balls of nickel or gold plated copper or copper alloy, i.e., microbumps 17, are then soldered to metal pads 18 having wettability arranged at the interconnection trace termination of the structure 10. The contact pad 19 of a bare die, i.e., an IC device 20, is then optically aligned with the bump 17 on a test base, and an appropriate pressure is applied, until the contact resistance between them is lowered to a specific level. A die exhibiting good test results is transferred to an appropriate waffle type back container, and defective dies are removed.
Inventors:
David John Pedder
Application Number:
JP2332593A
Publication Date:
December 17, 2001
Filing Date:
January 18, 1993
Export Citation:
Assignee:
Markoni Electronic Systems Limited
International Classes:
G01R1/073; G01R31/26; G01R31/28; H01L21/66; G01R1/067; (IPC1-7): G01R31/26; G01R1/067; H01L21/66
Domestic Patent References:
| JP63122140A | ||||
| JP2141681A | ||||
| JP3211745A | ||||
| JP251243A |
Attorney, Agent or Firm:
Nobuyuki Iida
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