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Patent Searching and Data


Title:
BASE LINE STABILIZING CIRCUIT
Document Type and Number:
Japanese Patent JPH04151589
Kind Code:
A
Abstract:

PURPOSE: To suppress the change of the level on an output signal line accompanying ON/OFF by symmetrically providing capacitor, resistors and switch elements on a feedback connection line with respect to an input terminal and synchronously subjecting both switch elements to continuity and discontinuity control.

CONSTITUTION: A condenser 3', a resistor 4' and an FET 8 are provided on the side of the feedback connection line of an operational amplifier 1 and connected so as to become symmetric to the constitution on the side of an input terminal where a condenser 3, a resistor 4 and an FET 8 are arranged. The FETs 8, 8' are used as switch elements. When a pulse is supplied to the input terminal 2, the FETs 8, 8' are together turned ON but a signal is sent to the FETs 8, 8' through a control signal line, the moment the pulse is supplied to turn the FETs 8, 8' OFF. A change is generated accompanying ON/OFF of the FETs 8, 8' but, since the FETs 8, 8' are respectively arranged on the mutually reverse polarity sides of an amplifier 1, the change is set off. Therefore, no change is generated on an output signal line accompanying ON/OFF. As a result, no error is almost generated in the peak of the output pulse of a stabilizing circuit.


Inventors:
HAYASHIDA SHINICHI
Application Number:
JP27574990A
Publication Date:
May 25, 1992
Filing Date:
October 15, 1990
Export Citation:
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Assignee:
JEOL LTD
International Classes:
G01R19/00; G01T1/17; G01T1/36; (IPC1-7): G01R19/00; G01T1/17; G01T1/36