PURPOSE: To quicken the discharge speed of a load capacitance at an output terminal of the Bi-CMOS logic circuit.

CONSTITUTION: A 2nd input circuit 80 of a NAND circuit provided with 1st, 2nd input circuits 70, 80, 1st and 2nd discharge circuits 90,100 and an output circuit 110 consists of a 1st series circuit 80a consisting of the series connection of nMOS 81, 82 and a 2nd series circuit 80b consisting of the series connection of nMOS 83, 84. The 1st and 2nd series circuits 80a, 80b are connected in parallel between a base of a pull-down bipolar transistor(TR) 112 and an output terminal 63. Thus, while the input capacitance is kept the same as that of a conventional circuit, the parasitic capacitance of the nMOS 81-84 is reduced. The charge charged at the output terminal 63 is outputted by charging the parasitic capacitance of the nMOS 81-84 and a base current is supplied to the TR 112 at a fast speed.