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Patent Searching and Data


Title:
BI-POLAR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS624367
Kind Code:
A
Abstract:

PURPOSE: To increase the junction capacitance of the collector-base with a small element area and to attain high integration, high reliability and high speed, by forming the base-collector junction vertically along a trench reaching the buried layer from the base region.

CONSTITUTION: After an N-type buried layer 11, an N-type epitaxial layer 13 and an element-separating oxide film 12 are formed on a P-type semiconductor substrate 10, a silicon oxide film 12A and a silicon nitride film 22 are formed on the region for the element to be formed, and a trench 24 reaching the epitaxial layer 13 is formed using photo resist 23 as a mask. After removing the photo resist 23, a P-type diffusion layer 14 is formed in the trench 24 and the trench 24 is etched using the nitride film 22 as a mask till it reaches the buried layer 11. An N-type diffusion layer 15 shallower than the P-type diffusion layer 14 is formed inside the trench and the trench is filled with polycrystalline silicon 18 having N-type impurities doped. Next, P-type impurities are ion- implanted to form a base region 16, and an N-type emitter region 17 is formed.


Inventors:
OI SUSUMU
Application Number:
JP14502985A
Publication Date:
January 10, 1987
Filing Date:
July 01, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/8222; H01L21/331; H01L21/8229; H01L27/06; H01L27/08; H01L27/10; H01L27/102; H01L29/72; H01L29/73; H01L29/732; (IPC1-7): H01L27/08; H01L27/10; H01L29/72
Attorney, Agent or Firm:
Uchihara Shin