To provide a clock group generating circuit with suppressed fluctuations in the duty factor of clock signals.

The clock group generating circuit has a PLL configuration including a VCO(voltage controlled oscillator) having inverter type delay stages whose buildup time and decay time can be controlled through the variation of bias voltages NBIAS and PBIAS used to drive power supply side and ground side current source transistors(TRs), and the VCO generates clock signals whose phases differ from each other. A circuit shown in Figure 3 represents a circuit that generates another bias voltage from one bias voltage, a replica circuit 12 at the delay stages outputs a replica signal Vrep in response to the bias voltages NBIAS and PBIAS and a differential amplifier circuit generates the bias voltage NBIAS or PBIAS where the replica signal Vrep is coincident with a reference signal VthL.