Title:
BICMOS INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3013784
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To cut the number of processes of forming a collector pulling-out region by introducing impurities simultaneously with the formation of other n-type regions.
SOLUTION: When a low concentration S-D region 8 and a high concentration S-D region 12a of an nMOS are formed, when a punch-through suppression n-type region 9 of a pMOS is formed and when a high-concentration n-type selective diffusion region 14 for a collector and an emitter region 16a of a bipolar transistor are formed, n-type impurities are introduced also into a collector pulling-out region at the same time, respectively, thereby forming the collector pulling-out region.
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Inventors:
Kayoko Sakamoto
Application Number:
JP22089396A
Publication Date:
February 28, 2000
Filing Date:
August 22, 1996
Export Citation:
Assignee:
NEC
International Classes:
H01L21/8249; H01L27/06; (IPC1-7): H01L21/8249; H01L27/06
Domestic Patent References:
| JP63292666A | ||||
| JP2276271A | ||||
| JP63260157A | ||||
| JP4179159A | ||||
| JP3246964A | ||||
| JP8293567A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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