Title:
BINARIZED NOISE SIGNAL GENERATOR
Document Type and Number:
Japanese Patent JP3480598
Kind Code:
B2
Abstract:
PURPOSE: To easily and effectively utilize a binarized noise signal for the field of digital technique by providing it from a certain specified kind of arithmetic rules.
CONSTITUTION: A clock circuit 3 is connected through a frequency divider circuit 4 for dividing the frequency of a clock pulse into the reciprocal-of-an- integer multiple to a main calculation circuit 1 and a sub-calculation circuit 2 executes arithmetic at an integral multiple speed of that of the main calculation circuit 1. An arithmetic signal (a) is inputted to a decision regulation circuit 5, coincidence detection circuit 6 and adder circuit 7, the decision regulation circuit 5 generates a binarized noise signal R according to the arithmetic signal (a), the coincidence detection circuit 6 compares the numerical value of the arithmetic signal (a) with that of a collate signal (b) and when both the numerical values are matched, a switching signal (d) is outputted. When the switching signal (d) is outputted, a switch S2 is turned on, a coefficient signal (f) is inputted to the adder circuit 7, and the added value is outputted as a signal K. Then, the signal K is inputted from a turned-on switch S3 through a switch S1 to the main calculation circuit 1 and the sub-calculation circuit 2, and this input is calculated as an initial value.
Inventors:
Shuji Nishimura
Kazuo Oguri
Kazuo Oguri
Application Number:
JP14653094A
Publication Date:
December 22, 2003
Filing Date:
June 28, 1994
Export Citation:
Assignee:
Netcom Sec Co., Ltd.
International Classes:
G06F7/58; H03K3/84; (IPC1-7): G06F7/58
Domestic Patent References:
| JP283619A | ||||
| JP461927U |
Attorney, Agent or Firm:
Kaneyuki Matsuura