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Title:
BINARY MULTI-DIGIT PHOTOELECTRIC ADDER
Document Type and Number:
Japanese Patent JPH10207567
Kind Code:
A
Abstract:

To make it possible to execute binary addition by four steps of gates or the like even when the number of digits is increased to several tens of digits by executing binary addition by a photoelectric circuit having no progressive carry.

Outputs from respective digit AND gates AB=10, 01 are inputted to an OR gate G1 and outputs from AND gates 11, 00 are inputted to an OR gate G0. An output from the gate G1 is inputted to an OR gate 1 when an AND gate St is ON and inputted to an OR gate 0 when an AND gate De is ON. An output from the gate G0 is inputted to the gate 0 when the gate St is ON and inputted to the gate 1 when the gate De is ON. An n-digit '11' signal is inputted to a Pmn (photodiode or the like) to turn on it, an output from the Pmn is inputted to a Dm (LED or LD), an output beam from the Dm is inputted to a Pm, and an output from the Pm is inputted to the m-digit AND gate De, and a NOT output is inputted to the AND gate St. On the other hand, a '00' signal of (m-1) to (n+1) digits (shown by j) is inputted to a gate Dj to emit the gate Dj. Thereby the Pmn is cut out. When the '11' signal is cut out, the gate St is turned on, and when the '11' signal is not cut out, the gate De is turned on. The number of electronic gates are four steps or the like (finely six steps).


Inventors:
SUGIMURA YUKICHI
Application Number:
JP4454897A
Publication Date:
August 07, 1998
Filing Date:
January 22, 1997
Export Citation:
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Assignee:
SUGIMURA YUKICHI
International Classes:
G06E1/04; H01L31/12; (IPC1-7): G06E1/04



 
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