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Patent Searching and Data


Title:
BIPOLAR PROM
Document Type and Number:
Japanese Patent JPS5952496
Kind Code:
A
Abstract:

PURPOSE: To attain high speed readout while simplifying the circuit, by including a row and column selecting circuit and a write circuit operating by receiving a row selecting level and transmitting a write signal to the column line.

CONSTITUTION: When all address signals from terminals A0WA7 are at low level, only TRs Q5, Q8 consisting the address decoder of the row/column selecting circuit are turned off. A column line W0 is brought to a high level of V00-2Vbe with the TRQ5 turned off. When a TRQ8 is turned off, a row line selecting switch TRQ10 is turned on. A write current is applied from a terminal 0 in this state. When the column line W0 is at high level, TRQ18WQ20 of the thyristor connection are turned on and a write current is given to the column line W0. Thus, the base-emitter junction of the transistors before write provided at the cross point between the column line W0 and the row line B0 are destroyed to form the diode constitution as shown in other columns and rows. Further, the transistors of the thyristor connection provided to other write circuits WA1WWA7 are turned off forcibly.


Inventors:
OONO NOBUHIKO
KATOU YUKIO
OGIUE KATSUMI
Application Number:
JP16099782A
Publication Date:
March 27, 1984
Filing Date:
September 17, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11C17/00; (IPC1-7): G11C17/00
Attorney, Agent or Firm:
Toshiyuki Usuda