Title:
ビットエラー検出方法および装置
Document Type and Number:
Japanese Patent JP7171732
Kind Code:
B2
Abstract:
Embodiments of this application disclose a bit error detection method and apparatus. The method includes: receiving a first result obtained by a sending device by performing BIP check on a sent first to-be-checked bit stream; performing BIP check on a received second to-be-checked bit stream to obtain a second result, where the second to-be-checked bit stream is a bit stream received by a receiving device after the first to-be-checked bit stream is transmitted; detecting a type of a control block in the second to-be-checked bit stream, and determining a third result based on impact of the type of the control block on a BIP check result; comparing the first result, the second result, and the third result; and if the first result is different from the second result, the first result is different from the third result, and the second result is different from a predetermined result, determining that a bit error occurs when the first to-be-checked bit stream is transmitted. According to this application, applicability and accuracy of BIP bit error detection can be improved.
Inventors:
徐 ▲麗▼
▲鐘▼ 其文
▲査▼ ▲敏▼
Lee Nissin
▲鐘▼ 其文
▲査▼ ▲敏▼
Lee Nissin
Application Number:
JP2020536127A
Publication Date:
November 15, 2022
Filing Date:
December 22, 2018
Export Citation:
Assignee:
HUAWEI TECHNOLOGIES CO.,LTD.
International Classes:
H04L1/00
Domestic Patent References:
| JP2012044574A | ||||
| JP2009164905A |
Attorney, Agent or Firm:
Shinya Mihiro
Susumu Nomura
Susumu Nomura
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