Title:
BIT MAP MEMORY CONTROLLER
Document Type and Number:
Japanese Patent JPS62105273
Kind Code:
A
Abstract:
PURPOSE:To facilitate LSI-implementation without increasing the data bus width of a component by providing a means which mixing the 1st circulation data and the 2nd circulation data which data in addresses including a destination area. CONSTITUTION:Barrel shifters 5-1 and 5-2 rotate input data under the control of a control circuit which is not shown in a figure according to the dot address value of a destination. Further, ALUs 7-1 and 7-2 performs logical operation among corresponding bits of input data of three systems. Then, a composing circuit 20 mixes the outputs of the ALUs 7-1 and 7-2 according to the value the readout head address of the destination to generate 32-bit data. Further, 32-bit data are arranged to 64 bits and 64-bit data is composed of 64-bit data read out of bit map memories 1-1-1-4 and outputted to the memories 1-1-1-4.
Inventors:
ONUMA SHOJI
Application Number:
JP24439185A
Publication Date:
May 15, 1987
Filing Date:
October 31, 1985
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G06F12/04; G06F3/153; G06F12/00; G06T3/20; (IPC1-7): G06F3/153; G06F12/00; G06F15/62
Attorney, Agent or Firm:
Kazuo Sato