PURPOSE: To perform bit order conversion at a high speed by performing the bit order conversion with hardware processing utilizing a data selector.

CONSTITUTION: A shift register 15 converts input picture data Din-S to parallel data. An input side data selector 16 takes the data supplied from the shift register 15 in the parallel so as to position the bit orders in the opposite direction each other respectively to A/B side data input A, B whatever serial format may be the input picture data Din-S. In this way, the bit order conversion is performed by the hardware processing by the data selector 16. Thus, the bit order conversion can be performed at a high speed.