PURPOSE: To detect the phase shifting between an input signal and a synchronizing clock through a low-speed operation by the use of the bit phase-locked circuit and to unnecessitate any adjustment for the delay amount inside the circuit.

CONSTITUTION: At a detecting circuit 20, the phases of the clock and the input data signal respectively selected by plural selectors 40-1 and 40-2 are compared and when the phase shift is larger than a previously decided value, the selected clock is changed by an output clock control circuit 30. Then, the clock is held by the fall of the input data signal and protected for m cycles.