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Patent Searching and Data


Title:
BIT RATE CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPH0983537
Kind Code:
A
Abstract:

To avoid the concentration of B-R cells in the ABR service of a bit rate control circuit in an ATM network.

A cell branching part 1 extracting the B-RM cell obtained by folding an F-RM cell transferred through a forward direction line and transmitting it to an inverse direction line 6, a cell generation/insertion part 2 generating the B-RM cell and inserting it into the inverse direction line 6 and a memory 3 storing the content of the B-RM cell for the respective logical lines of VPC and VCC are provided. A comparison arithmetic part 4 which OR-operates the congestion display bit C1 of the contents of the B-RM cell stored in the memory 3 with the arrived B-RM cell, for example, and updates the content of the memory 8 by the operated result and a transmission control part 5 controlling the cell generation/insertion part 2 and transmitting one B-RM cell when that the arriving number of the B-RM cells becomes a prescribed number is detected or that prescribed time is elapsed is detected are provided.


Inventors:
ISHIHARA TOMOHIRO
OKUDA MASAHITO
KUSAYANAGI MICHIO
SUDO TOSHIYUKI
Application Number:
JP23803595A
Publication Date:
March 28, 1997
Filing Date:
September 18, 1995
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04Q3/00; H04L12/28; H04L12/70; H04L12/801; H04L12/825; H04L12/911; (IPC1-7): H04L12/28; H04Q3/00
Attorney, Agent or Firm:
Shoji Kashiwaya (1 person outside)