PURPOSE: To reduce the load on a common control part and a processor for control by carrying out processing which covers both transmission and reception at one processing request every time transmission or reception is performed.
CONSTITUTION: When an FF13 is set with the start STM of a timer TM for bit synchronism, a transmission-side processing request SR0 is sent out, and consequently the common control part reads reception completion data RDB set in an FF10. Then, data SDB to be sent is set in the FF10. At this time, the FF13 is set with SDB set timing SSDB and the transmission processing request SR0 is turned off. The SDB set in the FF10 is then set in an FF11 with the next STM and sent out as transmit data SD to a circuit. At the same time, it is received as receive data RD, data set in an FF12 is set in the FF10, and the FF13 is set again to send out the SR0.
OGAWA YOSHIHISA
TAKAHASHI HIROSHI
