Title:
BLANKING PERIOD PROCESSING CIRCUIT
Document Type and Number:
Japanese Patent JPH01216682
Kind Code:
A
Abstract:
PURPOSE:To output a video data in a blanking period accurately in the same form as the input by setting a FF circuit when a BLK value is obtained in a part to be applied with video data processing, holding it till the succeeding BLK value is obtained and outputting the video data as it is in the blanking period. CONSTITUTION:A 1-frame memory output is branched into three, a signal passing through the calculation for a picture processing circuit 14, a signal passing through a delay circuit 15 having the same delay as that of the picture processing circuit 14 for bypassing and a signal passing through a circuit 16 detecting a blanking value. When a blanking value is detected by the detection circuit 16, one-pulse is fed to a FF 17, where a consecutive BLK signal 18 is obtained. A selector 19 is turned to the position of the delay circuit 15 for the blanking period only and the input data is outputted as it is as the video processing output 20 during horizontal and vertical BLK periods. Thus, stable blanking period is reproduced in any phase different from the input phase and various kinds of information of the blanking period is held till the output without being lost.
Inventors:
ONOZATO MASASHI
Application Number:
JP4118888A
Publication Date:
August 30, 1989
Filing Date:
February 24, 1988
Export Citation:
Assignee:
NEC CORP
International Classes:
H04N19/00; H04N19/85; (IPC1-7): H04N7/13
Attorney, Agent or Firm:
Sugano Naka