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Patent Searching and Data


Title:
BOOSTING CIRCUIT
Document Type and Number:
Japanese Patent JP2002191170
Kind Code:
A
Abstract:

To suppress the influence of a parasitic capacity and suppress the drop of an output voltage and the increase of power consumption, in the case of forming a boosting circuit on a single board together with other circuit elements.

The boosting circuit is provided with switches S11 and S21 between a contact N11 and a contact N12 which are supplied with a power voltage Vdd and between the contact N11 and a contact N13, a capacitor C1 between the contact N12 and the contact N13, a switches S12, S13, and S22 between the contact N13 and a ground terminal (GND), between the contact N12 and a contact N14, and between the contact N12 and a contact N15, a capacitor C2 between the contact N14 and the contact N15, and switches S23 and S14 between the contact N14 and the ground terminal and between the contact N15 and a load capacitor Cout, and a first connection state where the switches S11-S14 are set to be ON and the switches S21-S23 are set to be OFF, and a second connection state where the switches S11-S14 are set to be OFF and the switches S21-S23 are set to be OFF are set repeatedly.


Inventors:
NAKANISHI TAKAYUKI
Application Number:
JP2000388553A
Publication Date:
July 05, 2002
Filing Date:
December 21, 2000
Export Citation:
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Assignee:
CASIO COMPUTER CO LTD
International Classes:
H01L27/04; H01L21/822; H02M3/07; (IPC1-7): H02M3/07; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Kashima Hidemi