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Title:
BUFFER CIRCUIT MEANS FOR TEST EQUIPMENT AND METHOD AND ARRANGEMENT FOR CALIBRATION
Document Type and Number:
Japanese Patent JPH02201547
Kind Code:
A
Abstract:

PURPOSE: To improve the test and diagnosis performance of a microprocessor (μP)-base system by generating a synchronizing signal, which controls signal reception in both of a gated data buffer and a gated status buffer, in response to a signal indicating the operation state of a μP.

CONSTITUTION: A bus cycle state machine 200 subjects the signal, which reflects the operation state (status pin) of a UUT14 μP, to logical operation under the control of a main frame and generates a control signal which controls a synchronizing pulse generation state machine 202 which generates the synchronizing signal in response to the signal. The synchronizing signal directly controls gated buffers 214 and 216 to acquire the momentary state of the μP, so that the faulty μP or an improper state of a forced line can be efficiently diagnosed. Thus, the test and diagnosis performance of the μP-base electronic system is improved.


Inventors:
TOOMASU PII ROTSUKU
Application Number:
JP30451689A
Publication Date:
August 09, 1990
Filing Date:
November 22, 1989
Export Citation:
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Assignee:
FLUKE MFG CO JOHN
International Classes:
G06F11/22; G06F11/26; G06F11/267; G06F11/273; (IPC1-7): G06F11/22
Domestic Patent References:
JPS63269237A1988-11-07
JPS63241643A1988-10-06
Attorney, Agent or Firm:
Fukami Hisaro (2 outside)