Title:
BUFFER DEVICE
Document Type and Number:
Japanese Patent JPH11308280
Kind Code:
A
Abstract:
To realize a buffer device that selects a proper memory size automatically to minimize transmission delay.
Detection circuits 4, 5 detect a clock frequency on lines 2, 3, an arithmetic circuit 6 calculates a difference between both the frequencies and a switch 7 is used to select the capacity of a buffer memory 8 according to the above difference. Thus, an optimum memory capacity is set. A write circuit 9 writes data in the buffer memory 8 based on the clock of the line 2 and read-out circuit 10 reads data based on a clock on the line 3.
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Inventors:
SHINTO YASUNOBU
Application Number:
JP11123898A
Publication Date:
November 05, 1999
Filing Date:
April 22, 1998
Export Citation:
Assignee:
NEC CORP
International Classes:
H04L13/08; H04L7/00; H04L12/801; H04L12/861; H04L12/911; (IPC1-7): H04L13/08; H04L7/00; H04L12/56
Attorney, Agent or Firm:
Yanagi Kawa Shin
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