PURPOSE: To check the adequacy of the contents of an address array without any unnecessary time by providing respective arrays for data, control bits, and addresses independently, and reading a stored address at the timing of movement to the end of data and checking the adequacy.

CONSTITUTION: A buffer consists of the independent data array, control bit array 1, address array 2, etc., and when there is no data to be read, data from a main storage device is moved to the data array up to one block. When the final block is moved, the address registered in the 1st movement is read out and compared by a comparing circuit 3 with the high-order bits of the address in the main storage device of this block to check the adequacy of the address of the array 2; when no coincidence is obtained, a decision on a defective entry is made to perform error display. Consequently, the adequacy of the contents of the address array is checked without any waste time and a discrimination between the characteristic trouble of the address array itself and trouble in reading and writing is made.