PURPOSE: To surely output a burst data by adopting the constitution such that a synchronizing pulse and an operation clock are received and a time slot of an effective data is identified by using a counter.
CONSTITUTION: After a tetral counter 4 is cleared by the trailing of a clock CLK at first, the counter 4 starts counting clocks CLK, and if overflow takes place, a carry is raised and the counter 4 stops counting. A load pulse generating circuit 14 receives a CLK, an inverse of CLK and an SEL control signal, generates a load pulse from an AND gate 23 to set the load data to an M-adic down counter 24 and an M-adic counter 15 in a mask pulse generating circuit 15. Since the mask pulse is at logical 1 except when an output of an M-adic counter 25 is decoded, the level of the mask pulse except when a burst data VO3 is received is always logical 1 and there is no problem due to uncertain level.
KAJIWARA MASANORI
MASE HIDEKI
TOYOFUKU HIDETOSHI
Next Patent: DISAGREEMENT MECHANISM FOR DECIDING COINCIDENCE OF NUMERAL AND SWITCH WITH NUMERAL DISPLAY FUNCTION