To provide a bus access controller and an information processor with which the performance reduction of a CPU can be suppressed by efficiently performing access to the same memory even when clanging access time because of a difference in access types.

A bus access controller 30 is provided with a branch execution discriminating part 21, an intra-line word counter 22, an instruction/data selection control part 23, an instruction/data address selecting part 25, a bus access control signal generating part 31, an address decoder 32 and a CHGCLK generating part 33. Then, a signal for discriminating the access type of memory access for instruction fetch or memory access for data access is inputted and further, the division of an address space at the access destination provided by decoding an access address is inputted. Thus, information showing how many clocks are used for accessing a memory 34 is instructed and according to this information, the number of its own data access clocks is changed.