PURPOSE: To provide the bus arbitrating circuit which increases the processing speed without ignoring requests from modules having low priority levels by reducing the frequency in occurrence of bus arbitration.

CONSTITUTION: A bus arbitrating circuit 8 is provided with a priority level discriminating circuit 1 which discriminates a module having a high priority level in accordance with input of a bus use request signal, circuits 4 and 5 (a comparing circuit and a monitor circuit) which count the frequency with which the discrimination result of the priority level discriminating circuit 1 continuously has the same value, and a by-pass control circuit 2 which outputs the preceding discrimination result of the priority level discriminating circuit 1 as a bus use permission signal independently of discrimination of the circuit 1 in accordance with the next use request at the time when the counted value exceeds a prescribed value.