PURPOSE: To evade the unnecessary cache access stop of a processor and improve the performance by performing control so that neither a read request nor invalidation request to the same address from a system bus is issued until such time as response data are stored in the cache of the processor.

CONSTITUTION: In the case of receiving the invalidation request, for example, as a coherent request from the system bus 3 the bus controller 2 compares its block address with an invalidation buffer 4. When the address matches none of the addresses of the invalidation buffer 4, the invalidation request from the system bus 3 is sent out to the processor 1 and at the same time, the target address of the invalidation data is stored as the block address of the cache in the invalidation buffer 4. When the address matches one address, on the other hand, the invalidation request from the system bus 3 is not sent out to the processor 1.