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Title:
BUS OPEN PREVENTING CIRCUIT
Document Type and Number:
Japanese Patent JPH0512204
Kind Code:
A
Abstract:

PURPOSE: To cancel a period when the potential of a bus is unstable without using a resistor by detecting that any processors connected to one bus do not emit a bus acquirement request and driving the bus at every time.

CONSTITUTION: A refresh interval timer 3 outputs a refresh request signal at every prescribed time, and FF9 operates by the same clock signal as FF5. The output terminal of FF9 is connected to the respective input terminals of a NAND circuit 7 and an access control circuit 8. The output terminal of a NOR circuit 2 is connected to FF5. The output terminal of FF5 is connected to a driver 6 driving the bus BUS. The bus is driven in respective periods when a REQOP signal becomes 'H' in spite of the refresh request signal REFRQ from the timer 3 by constituting the input signal of FF5 only by the output signal of the NOR circuit 2. Thus, the instability of potential when the bus is not used is cancelled.


Inventors:
ABO KENICHI
OGURA KIMINARI
KIKUCHI WATARU
YAMAGUCHI TATSUYA
Application Number:
JP15939391A
Publication Date:
January 22, 1993
Filing Date:
July 01, 1991
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F13/00; G06F13/42; (IPC1-7): G06F13/00; G06F13/42
Attorney, Agent or Firm:
Takashi Honma



 
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