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Title:
BUS STRUCTURE OF SUBSTRATE MOUNTED WITH INTEGRATED CIRCUIT, STANDING WAVE SUPPRESSION METHOD THEREFOR, AND BUS RESONANCE FREQUENCY ANALYSIS METHOD
Document Type and Number:
Japanese Patent JP2006262006
Kind Code:
A
Abstract:

To provide a bus structure of a substrate mounted with an integrated circuit, the bus structure which reduces the limit of the transmission speed and the limit of performance improvement and achieves reduction in power consumption.

LSI/IC chips 11-19, mounted on a mother board substrate, are connected by a star-type bus in which the wiring patterns of an equal length are formed from one optional point. Even if the star-type bus is adopted, there is a combination not to be practical by resonance (standing waves). Then, as a method of generating signals (opposite standing waves) having characteristics opposite to those of the standing waves, in order to suppress a resonance peak, a λ/4 open stab 21 is extended from a center point, thereby the counter is applied to the peak frequency and the resonance peak is suppressed. Also, an isolation resistor 22 is inserted to the wiring pattern, where the peak frequency is generated and it is made to look as if the bus is not connected.


Inventors:
AOKI YOSHIRO
YAMADA TAKASHI
OTOMO HISASHI
Application Number:
JP2005075958A
Publication Date:
September 28, 2006
Filing Date:
March 16, 2005
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H03K19/0175; H03K19/00
Domestic Patent References:
JP2001175373A2001-06-29
JP2001333115A2001-11-30
JP2006074431A2006-03-16
JP2002259481A2002-09-13
JP2004007657A2004-01-08
JPH07212406A1995-08-11
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto