PURPOSE: To perform the data transfer of equipment for which access time is desired to be shortened by interrupting a transfer cycle being executed and executing the transfer cycle of equipment with higher priority when the equipment with priority higher than that of the equipment executing the data transfer, issues a bus use request.
CONSTITUTION: Plural I/O equipment 1a-1d, a bus 2 which connects them, and a bus controller 3 which controls the bus use right of the plural I/O equipment 1a-1d connected to the bus 2 are provided. The priority for the use of the bus 2 is set on the plural equipment 1a-1d, and the bus controller 3 interrupts the transfer cycle of the equipment 1a-1d executing the data transfer when the equipment 1a-1d with priority higher than that of the equipment 1a-1d that is a transfer origin executing the data transfer by using the bus 2 issues the bus use request, and executes the transfer cycle of the equipment 1a-1d with higher priority. After the transfer cycle is completed, an interrupted transfer cycle is restarted.
JPS62173560 | MEMORY ACCESS CONTROL CIRCUIT |
JPS6459558 | DATA PROCESSING SYSTEM |
SHIBATA NAOAKI
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