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Patent Searching and Data


Title:
BUS TRANSFER SYSTEM
Document Type and Number:
Japanese Patent JPH06103222
Kind Code:
A
Abstract:

PURPOSE: To prevent the processing capacity of a central processing unit(CPU) from being reduced by storing sent address and data in the CPU, and at the time of detecting an error in either one of received address and data, requesting resending of the data.

CONSTITUTION: The CPU transmits an address and data to an address/data storage control device 2 and stores the address and data in an address/data storing means 4. When an address/data error detecting means 6 detects the existence of an error such as a parity error in the address or data received by the device 2, a resending request control means 7 transmits a resending request to a resending control means 5 in the CPU 1 and the means 5 transmits an address/data transmitting signal 15 to the means 4, which resends correct data corresponding to the error data to the device 2. Thereby, the correct data can be written in a main storage device 3 without executing interrupting processing.


Inventors:
BABA YUJI
Application Number:
JP10010192A
Publication Date:
April 15, 1994
Filing Date:
April 21, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/14; G06F13/16; G06F13/36; (IPC1-7): G06F13/16; G06F11/14; G06F13/36
Domestic Patent References:
JPH02264337A1990-10-29
JPS4962039A1974-06-15
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)