Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
BUS USE RIGHT ARBITRATION CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH0612366
Kind Code:
A
Abstract:

PURPOSE: To provide the bus use right arbitration control system which eliminates the dead cycle of a bus use right arbitration cycle and improve the data transfer efficiency of a system bus as to a bus use arbitration control system for a decentralized processing system wherein plural processors are connected to a system bus and transfer data to one another.

CONSTITUTION: The processors 10 are connected to one another through the system bus 1, a system bus allocating circuit 30 arbitrates a right to use the bus, and the processors 10 transfer data to one another. This decentralized processing system is constituted by providing a processor logical connection information setting means 50 which can optionally set information showing which processor requests the right to use the system bus 1 and a processor number discriminating and generating means 40 which successively sends out processor numbers set by the processor logical connection information setting means 50 to the system bus 1 in the system bus allocating circuit 30.


Inventors:
YAMAGUCHI TETSUO
Application Number:
JP20508891A
Publication Date:
January 21, 1994
Filing Date:
August 15, 1991
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
FUJITSU COMMUNICATION SYST
International Classes:
G06F13/366; G06F13/38; G06F15/16; G06F15/177; H04L12/40; H04Q3/58; (IPC1-7): G06F13/366; G06F13/38; G06F15/16; H04L12/40; H04Q3/58
Attorney, Agent or Firm:
Fujishima Ijima (1 outside)



 
Next Patent: キャリアテープ