Title:
容量結合を利用したCMOSのAD変換回路
Document Type and Number:
Japanese Patent JP4255486
Kind Code:
B2
Inventors:
Yoshihiro Miyamoto
Application Number:
JP2006222157A
Publication Date:
April 15, 2009
Filing Date:
August 17, 2006
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03M1/44; H03K5/08; H03K19/20; H03M1/74
Domestic Patent References:
| JP3048528A | ||||
| JP7131352A | ||||
| JP57124933A | ||||
| JP64081082A | ||||
| JP8125152A | ||||
| JP8204563A | ||||
| JP8102674A |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku