Title:
CACHE CONTROLLING APPARATUS, INFORMATION PROCESSING APPARATUS, AND CACHE CONTROLLING PROGRAM
Document Type and Number:
Japanese Patent JP2010237739
Kind Code:
A
Abstract:
To reduce the occurrence probability of a soft error in a cache memory.
A cache memory 30 is managed using a tag memory 40, and utilized by a write-through method. The cache controlling apparatus includes a supervising section 51A adapted to supervise accessing time to the cache memory 30, and a refreshing section 51B adapted to read data on one or more cache lines of the cache memory 30 from the main memory again in response to the result of the supervision by the supervising section 51A, and retain the read data into the cache memory.
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Inventors:
MATSUI NORIYUKI
Application Number:
JP2009081888A
Publication Date:
October 21, 2010
Filing Date:
March 30, 2009
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F12/08; G06F12/00; G06F12/16
Domestic Patent References:
| JP2005092311A | 2005-04-07 |
Other References:
JPN6013010261; Ｖｉｌａｓ Ｓｒｉｄｈａｒａｎ ｅｔ ａｌ．: 'Ｒｅｄｕｃｉｎｇ Ｄａｔａ Ｃａｃｈｅ Ｓｕｓｃｅｐｔｉｂｉｌｉｔｙ ｔｏ Ｓｏｆｔ Ｅｒｒｏｒｓ' ＩＥＥＥ ＴＲＡＮＳＡＣＴＩＯＮ ＯＮ ＤＥＰＥＮＤＡＢＬＥ ＡＮＤ ＳＥＣＵＲＥ ＣＯＭＰＵＴＩＮＧ ＶＯＬ．３， ＮＯ．４, 20061102, Ｐ．３５３-Ｐ．３６４, ＩＥＥＥ Ｃｏｍｐｕｔｅｒ Ｓｏｃｉｅｔｙ
Attorney, Agent or Firm:
Yu Sanada
Masahisa Yamamoto
Masahisa Yamamoto